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Volumn 1, Issue , 2004, Pages

Power efficient fully differential low-voltage two stage class AB/AB OP-AMP architectures

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITIVE LOADS; CLOCK FREQUENCIES; GATE SOURCE VOLTAGE DROP; NONLINEAR SETTLING TIMES;

EID: 4344654053     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (7)

References (7)
  • 1
    • 0032187835 scopus 로고    scopus 로고
    • Compact low-voltage power efficient operational amplifier cells for VLSI
    • Oct.
    • K. de Langen, J.H. Huising, "Compact Low-voltage Power Efficient Operational Amplifier Cells for VLSI", IEEE J. of Solid State Circuits Vol. SC-33, No. 10, Oct. 1998, pp. 1482-1496
    • (1998) IEEE J. of Solid State Circuits , vol.SC-33 , Issue.10 , pp. 1482-1496
    • De Langen, K.1    Huising, J.H.2
  • 2
  • 5
    • 0034998524 scopus 로고    scopus 로고
    • A new class AB differential Input stage for implementation of low voltage high slew rate op-amps and linear transconductors
    • May 6-9, Sidney Australia
    • J. Ramírez-Angulo, R. Gonzalez-Carvajal, A. Torralba and Carlos Nieva, "A new class AB differential Input stage for implementation of low voltage high slew rate op-amps and linear transconductors," IEEE ISCAS, May 6-9, 2001 Sidney Australia, pp. I-671-I-674.
    • (2001) IEEE ISCAS
    • Ramírez-Angulo, J.1    Gonzalez-Carvajal, R.2    Torralba, A.3    Nieva, C.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.