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Volumn 1, Issue , 2004, Pages
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Power efficient fully differential low-voltage two stage class AB/AB OP-AMP architectures
a a b c |
Author keywords
[No Author keywords available]
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Indexed keywords
CAPACITIVE LOADS;
CLOCK FREQUENCIES;
GATE SOURCE VOLTAGE DROP;
NONLINEAR SETTLING TIMES;
CMOS INTEGRATED CIRCUITS;
COMPUTER SIMULATION;
ELECTRIC CURRENTS;
ELECTRIC NETWORK TOPOLOGY;
ELECTRIC POTENTIAL;
TRANSISTORS;
OPERATIONAL AMPLIFIERS;
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EID: 4344654053
PISSN: 02714310
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
Times cited : (7)
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References (7)
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