Compact CMOS linear transconductor and four-quadrant analogue multiplier

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 1, Issue , 2004, Pages

  Panovic, Mladen ^a   Demosthenous, Andreas ^a  

^a UNIVERSITY COLLEGE LONDON   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POTENTIAL; ELECTRON MULTIPLIERS; GATES (TRANSISTOR); NETWORKS (CIRCUITS); SIGNAL PROCESSING; TRANSCONDUCTANCE;

ANALOG MULTIPLIERS; COMPUTATIONAL CELLS; SQUARE-LAW FUNCTION;

CMOS INTEGRATED CIRCUITS;

EID: 4344651227     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

1. M. Ismail and T. Feiz, Eds., Analog VLSI: Signal and Information Processing, McGraw-Hill, 1994.
2. A. Nedungadi, and T. R Viswanathan, "Design of linear CMOS transconductanoe elements," IEEE Trans. Circuits Syst., vol. 31, pp. 891-894, Oct. 1984.
3. H.-J. Song, and C.-K. Kim, "A MOS four-quadrant analogue multiplier using simple two-input squaring circuits with source followers," IEEE J. Solid-State Circuits, vol. 25, pp. 841-848, June 1990.
4. T. L. Viswanathan, "CMOS transconductance element," Proc. IEEE, vol. 74, pp. 222-224, 1986.
5. M. F. Li, X. Chen, and Y. C. Lim, "Linearity improvement of CMOS transconductors for low supply applications," IEE Electron. Lett., vol. 29, pp. 1106-1107, June 1993.
6. E. Seevink, and R. F. Wassenaar, "A versatile CMOS linear tranconductor/square-law function circuit," IEEE J. Solid-State Circuits, SC-22, pp. 366-377, June 1987.
7. J. Ramirez-Angulo, et al., "The flipped voltage follower: a useful cell for low-voltage low-power circuit design", in Proc. ISCAS'02, vol. 3, pp. 615-618, Phoenix, AZ, 2002.
8. B.-D. Liu, C.-Y. Chen, and J.-Y. Tsao, "A modular current-mode classifier circuit for template matching application," IEEE Trans. Circuits and Syst.-II, vol. 47, pp. 145-151, Feb. 2000.
9. G. Cauwenberghs and V. Pedroni, "A low-power CMOS analog vector quantizer," IEEE J. Solid-State Circuits, vol. 32, pp. 1278-1283, Aug. 1997.
10. A. Tomasini et al., "B/W adaptive image grabber with analog motion vector estimator at 0.3 GOPS," in Proc. ISSCC'96, pp. 94-95, San Fransisco, CA, 1996.
11. G. Han and E. Sanchez-Sinencio, "CMOS transconductance multipliers: a tutorial", IEEE Trans. Circuits and Syst.-II, vol. 45, pp. 1550-1563, Dec. 1998.
12. K. Kimura, "Analysis of an MOS four-quadrant analog multiplier using two-input squaring circuits with source followers," IEEE Trans. Circuits Syst.-I, vol. 41, pp. 72-75, Jan. 1994.