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Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 2, Issue , 2004, Pages

Atechnique to deskew differential PCB traces

(2) Atrash, Amer Hani a Butka, Brian a

a GEORGIA INSTITUTE OF TECHNOLOGY (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COUNTER-CONTROLLED DELAY; DESKEWING SYSTEM; DIFFERENTIAL SIGNALS; NEGATIVE TRACES;

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DELAY CIRCUITS; DIGITAL SIGNAL PROCESSING; ITERATIVE METHODS; RESISTORS;

PRINTED CIRCUIT BOARDS;

EID: 4344647598 PISSN: 02714310 EISSN: None Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper

Times cited : (6)

References (8)

1
- 0027876185
- A method for skew-free distribution of digital signals using matched variable delay lines
- T. Knight and H. Wu, "A Method for Skew-Free Distribution of Digital Signals Using Matched Variable Delay Lines," Symposium on VLSI Circuits, pp. 19-20, 1993.
- (1993) Symposium on VLSI Circuits , pp. 19-20
- Knight, T.¹ Wu, H.²

2
- 0005387611
- Low-skew clock generator with dynamic impedance and delay matching
- A. Balatsos and D. Lewis, "Low-Skew Clock Generator with Dynamic Impedance and Delay Matching," IEEE International Solid-State Circuits Conf., pp. 182-183, 1999.
- (1999) IEEE International Solid-state Circuits Conf. , pp. 182-183
- Balatsos, A.¹ Lewis, D.²

3
- 0033116470
- Low-power clock-deskew buffer for high-speed digital circuits
- April
- S. Liu, J. Lee, and H. Tsao, "Low-Power Clock-Deskew Buffer for High-Speed Digital Circuits," IEEE J. Solid-Stale Circuits, vol.34, no.4, pp.554-558, April 1999.
- (1999) IEEE J. Solid-stale Circuits , vol.34 , Issue.4 , pp. 554-558
- Liu, S.¹ Lee, J.² Tsao, H.³

4
- 0035247388
- A one-wire approach for skew-compensating clock distribution based on bidirectional techniques
- February
- C. Yang and S. Liu, "A One-Wire Approach for Skew-Compensating Clock Distribution Based on Bidirectional Techniques," IEEE J. Solid-State Circuits, vol.36, no.2, pp.266-272, February 2001.
- (2001) IEEE J. Solid-state Circuits , vol.36 , Issue.2 , pp. 266-272
- Yang, C.¹ Liu, S.²

5
- 0034246929
- Clock-deskew buffer using a SAR-controlled delay-locked loop
- August
- G. Dehng, J. Hsu, C. Yang, and S. Liu, "Clock-Deskew Buffer Using a SAR-Controlled Delay-Locked Loop," IEEE J. Solid-State Circuits, vol.35, no.8, pp.1128-1136, August 2000.
- (2000) IEEE J. Solid-state Circuits , vol.35 , Issue.8 , pp. 1128-1136
- Dehng, G.¹ Hsu, J.² Yang, C.³ Liu, S.⁴

6
- 0028485599
- A dynamic clock synchronization technique for large systems
- August
- D. Brueske and S. Embabi, "A Dynamic Clock Synchronization Technique for Large Systems," IEEE Trans. Comp., Packag., Manufact. Technol. B., vol.17, no.3, pp.350-360, August 1994.
- (1994) IEEE Trans. Comp., Packag., Manufact. Technol. B. , vol.17 , Issue.3 , pp. 350-360
- Brueske, D.¹ Embabi, S.²

7
- 4344658029
- The design of 8-Bit CMOS digital to analog converter
- Nov
- G. Tan, B. Surparjo, R. Wagiran, and R. Sidek, "The Design of 8-Bit CMOS Digital to Analog Converter," 2000 IEEE International Conf. on Semiconductor Electronics, Nov, 2000, pp. 231-234.
- (2000) 2000 IEEE International Conf. on Semiconductor Electronics , pp. 231-234
- Tan, G.¹ Surparjo, B.² Wagiran, R.³ Sidek, R.⁴

8
- 0029216786
- Circuit technique for skew-free clock distribution
- H. Sutoh, K. Yamakoshi, and M. Ino, "Circuit Technique for Skew-Free Clock Distribution," IEEE Custom Integrated Circuits Conf., pp.163-166, 1995.
- (1995) IEEE Custom Integrated Circuits Conf. , pp. 163-166
- Sutoh, H.¹ Yamakoshi, K.² Ino, M.³

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.