Simulation and inverse modeling of TEOS deposition processes using a fast level set method

International Conference on Simulation of Semiconductor Processes and Devices, SISPAD

Volumn 2002-January, Issue , 2002, Pages 191-194

  Heitzinger, C ^a   Fugger, J ^b   Haberlen O ^b   Selberherr, S ^a  

^a INSTITUTE FOR MICROELECTRONICS   (Austria)

^b INFINEON TECHNOLOGIES AUSTRIA AG   (Austria)

Author keywords

Computational modeling; Etching; Filling; Inverse problems; Level set; Manufacturing processes; Predictive models; Scanning electron microscopy; Silicon; Virtual manufacturing

Indexed keywords

AGILE MANUFACTURING SYSTEMS; DEPOSITION; DROP BREAKUP; ETCHING; FILLING; LEVEL MEASUREMENT; MANUFACTURE; NUMERICAL METHODS; SCANNING ELECTRON MICROSCOPY; SEMICONDUCTOR DEVICES; SEMICONDUCTOR STORAGE; SILICON; SILICON OXIDES;

COMPUTATIONAL MODEL; LEVEL SET; MANUFACTURING PROCESS; PREDICTIVE MODELS; VIRTUAL MANUFACTURING;

INVERSE PROBLEMS;

EID: 4344642942     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SISPAD.2002.1034549     Document Type: Conference Paper

References (5)

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4. J. Sethian, Level Set Methods and Fast Marching Methods (Cambridge University Press, Cambridge, 1999).
5. C. Heitzinger and S. Selberherr, Microelectronics Journal (Design, Modeling and Simulation in Microelectronics and MEMS; Smart Electronics and MEMS) 33, 61 (2002).