Memory-based low density parity check code decoder architecture using loosely coupled two data-flows

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 2, Issue , 2004, Pages

  Kang, Se Hyeon ^a   Park, In Cheol ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CODE DIVISION MULTIPLE ACCESS; DATA STORAGE EQUIPMENT; ERRORS; MATRIX ALGEBRA; PROBLEM SOLVING; TURBO CODES; VLSI CIRCUITS;

BIPARTITE GRAPH; DATA FLOW; LOW DENSITY PARITY CHECK (LDPC); MESSAGE PASSING ALGORITHMS;

DECODING;

EID: 4344637836     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

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