A low-power, hard-decision analogue convolutional decoder using the modified feedback decoding algorithm

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 4, Issue , 2004, Pages

  Tomatsopoulos, Billy ^a   Demosthenous, Andreas ^a  

^a UNIVERSITY COLLEGE LONDON   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BROADCASTING; COMPUTATIONAL COMPLEXITY; COMPUTER HARDWARE; DECODING; FEEDBACK CONTROL; SYNCHRONIZATION; TELEMETERING;

DATA RATES; MODIFIED FEEDBACK DECODING ALGORITHM (MFDA); POWER DISSIPATION; VITERBI DECODER (VD);

CMOS INTEGRATED CIRCUITS;

EID: 4344614041     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. A. J. Viterbi, "Error Bounds for convolutional codes and an asymptotically optimum decoding algorithm," IEEE Trans. Info. Theory, vol. IT-13, pp. 260-269, Apr. 1967.
2. K. Taura, et al., "A Digital audio broadcasting (DAB) receiver", IEEE Trans. Consumer Electron., vol. 42, pp. 322-327, Aug. 1996.
3. I. Kang and A. N. Willson Jr., "Low-power Viterbi decoder for CDMA mobile terminals", IEEE J. Solid-State Circuits, vol. 33, pp. 473-482, Mar. 1998.
4. M. H. Shakiba, D.A. Johns, and K. W. Martin, "An integrated 200-MHz 3.3-V BiCMOS class-IV partial-response analog Viterbi decoder", IEEE J. Solid-State Circuits, vol. 33, pp. 61-75, Jan. 1998.
5. A. Demosthenous and J. Taylor, "A 100-Mb/s 2.8-V CMOS current-mode analog Viterbi decoder," IEEE J. Solid-State Circuits, vol. 37, pp. 904-910, Jul. 2002.
6. A. Demosthenous, C. Verdier, and J. Taylor, "A new architecture for low power analogue convolutional decoders", in Proc. ISCAS'97, Hong Kong, vol. 1, pp. 37-40, June 1997.
7. B. Tomatsopoulos and A. Demosthenous "Further simulation results of the modified feedback decoding algorithm for convolutional Codes", in Proc. ECCTD'03, Krakow, Poland, vol. 2, pp. 357-360, Sep. 2003.