A 3.6-Gb/s 340-mW 16:1 pipe-lined multiplexer using 0.18 μm SOI-CMOS technology

IEEE Journal of Solid-State Circuits

Volumn 35, Issue 5, 2000, Pages 751-756

  Nakura, Torn ^a   Ueda, Kimio ^a   Kubo, Kazuo ^a   Matsuda, Yoshio ^a   Mashiko, Koichiro ^a   Yoshihara, Tsutomu ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

Multiplexer (mux); PECL; Phase shift; Pipeline; Selector; SOI

Indexed keywords

EID: 4344612460     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.841503     Document Type: Article

References (9)

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