SCOPUS 정보 검색 플랫폼

Plating and Surface Finishing

Volumn 90, Issue 11, 2003, Pages 40-45

Designs for minimizing resistive substrate effects on wafer metallization

(3) Cao, Yang a Lee, Jong MIn b West, Alan C c

a INTEL CORPORATION (United States)

b Och Spine at New York Presbyterian Hospitals (United States)

c Columbia University ^* (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTROLYTE CONDUCTIVITY; RESISTIVE SUBSTRATE EFFECTS; WAFER METALLIZATION;

ANODES; BOUNDARY ELEMENT METHOD; COMPUTER SIMULATION; COPPER; ELECTRIC CONDUCTIVITY; ELECTRIC FIELDS; ELECTROLYSIS; ELECTROLYTES; ELECTROLYTIC CELLS; SEMICONDUCTOR MATERIALS; SUBSTRATES; VOLTAGE CONTROL;

ELECTROPLATING;

EID: 4344612140 PISSN: 03603164 EISSN: None Source Type: Trade Journal
DOI: None Document Type: Article

Times cited : (14)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.