Modeling of the impact of the current source output impedance on the SFDR of current-steering CMOS D/A converters

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 1, Issue , 2004, Pages

  Chen, Tao ^a   Gielen, Georges ^a  

^a UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC IMPEDANCE; ELECTRIC POTENTIAL; ELECTRIC RESISTANCE; MATHEMATICAL MODELS; TRANSCONDUCTANCE; TRANSISTORS;

CURRENT STEERING; PARASITIC CAPACITANCES; SIGNAL FREQUENCY; SWITCHING TRANSISTORS;

DIGITAL TO ANALOG CONVERSION;

EID: 4344587180     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. A. Van den Bosch, M. Steyaert and W. Sansen, "SFDR-Bandwidth Limitations for High Speed High Resolution Current Steering CMOS D/A Converters," in International Conference on Electronics, Circuits and Systems, vol. 3, pp. 1193-1196, Sept., 1999
2. T. Miki, Y. Nakamura, K. Okada and Y. Horiba, "Transient Analysis of Switched Current Sources," IEICE Trans. Electron, vol. E75-C, pp. 288-296, Mar. 1999
3. 2 Random Walk CMOS DAC," IEEE J. Solid-State Circuits, vol. 34, pp. 1708-1718, Dec. 1999
4. J.Bastos, A.M.Marques, M.Steyaert and W.Sansen, "A 12-Bit Intrinsic Accuracy High-Speed CMOS DAC," IEEE J. Solid-State Circuits, vol. 33, pp. 1959-1969, Dec. 1998
5. Y. Cong and R. Geiger, "A 1.5V 14b 100MS/s Self-Calibrated DAC," in IEEE ISSCC 2003 Session 7/Dacs AND AMPs/Paper 7.2.
6. J. Hyde, T. Humes, C. Diorio, M. Thomas and M. Figueroa, "A 300-MS/s 14-bit Digital-to Analog Converter in Logic CMOS," IEEE J. Solid-State Circuits,vol. 38,pp. 734-740, May. 2003.