The design of a differential CMOS charge pump for high performance phase-locked loops

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 4, Issue , 2004, Pages

  Terlemez, Bortecene ^a   Uyemura, John P ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA COMMUNICATION FEEDBACK; PHASE FREQUENCY DETECTORS; VOLTAGE CONTROLLED OSCILLATORS (VCO);

CAPACITORS; DIFFERENTIAL EQUATIONS; ERROR ANALYSIS; INTEGRATED CIRCUIT LAYOUT; PHASE LOCKED LOOPS; PUMPS; VOLTAGE MEASUREMENT;

CMOS INTEGRATED CIRCUITS;

EID: 4344579124     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. B. Razavi, RF Microelectronics, Prentice Hall PTR, first edition.
2. P. S. Stetson, Design Considerations for Low Phase Jitter Clock Generators, Ph.D. thesis, University of Michigan, Michigan, 1998.
3. P. Larsson, "A 2-1600-MHz CMOS clock recovery PLL with low-Vdd capability," IEEE J. Solid-State Circuits, vol. 34, pp. 1951-1960, 1999.
4. C.-M Hung and K. K. O, "A fully integrated 1.5-V 5.5-GHz CMOS phase-locked loop," IEEE J. Solid-State Circuits, vol. 37, pp. 521-525, 2002.
5. M. Tiebout, "Low-power, low-phase noise differentially tuned quadrature VCO design in standard CMOS," IEEE J. Solid-State Circuits, vol. 36, pp. 1018-1024, 2001.