A leakage estimation and reduction technique for scaled CMOS logic circuits considering gate-leakage

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 2, Issue , 2004, Pages

  Rahman, Hafijur ^a   Chakrabarti, Chaitali ^a  

^a Arizona State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

LEAKAGE ESTIMATION; LEAKAGE POWER REDUCTION; MINIMUM LEAKAGE VECTOR (MLV);

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; COMPUTER SOFTWARE; ELECTRON TUNNELING; LEAKAGE CURRENTS; MOSFET DEVICES;

LOGIC CIRCUITS;

EID: 4344565875     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

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2. K. Cao, et. al. 'BSIM4 Gate Leakage Model Including Source Drain Partition,' IEDM, pp. 815-818, 2000.
3. T. Y. Chen, J. Chen, P. K. Ko, C. Hu, "The Impact of Gate-induced Drain Leakage Current on MOSFET Scaling,' Tech. Digest of IEDM, pp. 718-721, 1987.
4. D. Lee, W. Kwong, D. Blaauw, and D. Sylvester, 'Analysis and Minimization Techniques for Total Leakage Considering Gate Oxide Leakage,' In Proc. DAC, pp. 175-180, June 2003.
5. R.M. Rao, J.L. Burns, A. Devgan and R.B. Brown, 'Efficient Techniques for Gate Leakage Estimation,' In Proc. ISLPED, pp. 100-103, August 2003.
6. M. Johnson, D. Somasekhar, and K. Roy, 'Models and Algorithms for Bounds on Leakage in CMOS Circuits,' IEEE Trans. on CAD of Integrated Circuits And Systems, Vol 18, No. 6, pp. 714-725, June 1999.
7. Y. Ye, S. Borker, and V. De, 'A New Technique for Standby Leakage Reduction in High-Performance Circuits,' Symposium on VLSI Circuits, pp. 40-41.9, 1998.
8. A. Abdollahi, F. Fallah, and M. Pedram, 'Runtime Mechanisms for Leakage Current Reduction in CMOS VLSI Circuits,' In Proc. ISLPED, pp. 213-218, Aug. 2002.