Optimizations of a hardware decoder for deep-Space optical communications

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 55, Issue 2, 2008, Pages 644-658

  Cheng, Michael K ^a   Nakashima, Michael A ^a   Moision, Bruce E ^a   Hamkins, Jon ^a  

^a CALIFORNIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Cyclic redundancy check (CRC); Field programmable gate array (FPGA) implementation; FPGA implementation; Optical communications; Quadratic polynomial interleaver; Turbo decoding

Indexed keywords

APPROXIMATION THEORY; COMPUTER HARDWARE; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); OPTICAL COMMUNICATION; OPTIMIZATION; POLYNOMIALS; PULSE MODULATION;

CYCLIC REDUNDANCY CHECK; QUADRATIC POLYNOMIAL INTERLEAVER; TURBO DECODING;

DECODING;

EID: 42949123005     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2007.913733     Document Type: Article

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