Salicide-Bridged trench capacitor with a Double-Sacrificial-Si3N4-Sidewall (DSS) for high-performance logic-embedded DRAMs

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 1997, Pages 37-40

  Togo, M ^a   Iwao, S ^a   Nobusawa, H ^a   Hamada, M ^a   Yoshida, K ^a   Yasuzato, N ^a   Tanigawa, T ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DYNAMIC RANDOM ACCESS MEMORY (DRAM); SUBSTRATE PLATE TRENCH (SPT) CAPACITOR;

CAPACITORS; CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; LOGIC GATES; SEMICONDUCTING SILICON COMPOUNDS;

RANDOM ACCESS STORAGE;

EID: 4243989093     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)