2.9 μm2 embedded SRAM cell with co-salicide direct-strap technology for 0.18 μm high performance CMOS logic

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 1997, Pages 847-850

  Noda, K ^a   Matsui, K ^a   Inoue, K ^a   Itani, T ^a   Iwasaki, H ^a   Urabe, K ^a   Miyamoto, H ^a   Tokashiki, K ^a   Kawamoto, H ^a   Satoh, M ^a   Yoshida, K ^a   Kishimoto, K ^a   Koyanagi, K ^a   Tanigawa, T ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CO SALICIDE DIRECT STRAP TECHNOLOGY; STATIC RANDOM ACCESS MEMORY (SRAM);

CMOS INTEGRATED CIRCUITS; DIFFUSION IN SOLIDS; ETCHING; INTEGRATED CIRCUIT MANUFACTURE; LOGIC CIRCUITS;

RANDOM ACCESS STORAGE;

EID: 4243617927     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)