A 1.4ns/64kb RAM with 85ps/3680 Logic Gate Array

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 1989, Pages

  Kimoto, Masayoshi ^a   Shimizu, Hiroshi ^a   Ito, Yoshito ^a   Kohno, Kazuyuki ^a   Ikeda, Motohisa ^a   Deguchi, Tatsuya ^a   Fukuda, Nobutaka ^a   Ueda, Koichiro ^a   Harada, Shigeki ^a   Kubota, Katsuhisa ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ACCESS TIME; BIPOLAR TECHNOLOGY; GRID ARRAYS; PROPAGATION DELAYS;

INTEGRATED CIRCUITS;

LOGIC GATES;

EID: 4243198286     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.1989.56765     Document Type: Conference Paper

References (2)

1. K.Ueno et al.: "A sub-40ps ECL Circuit at a Switching Current of 1.28mA", International Electron Device Meeting, Tech. Digest, pp. 371-314(1987)
2. Y. Sugo etal.: " An ECL 2.8ns 16k RAM with 1.2k GATE ARRAY",ISSCC Digest of technical papaers, pp256 257;Feb., 1986