3.3 v BiNMOS technology using NPN transistors without buried layers

Technical Digest - International Electron Devices Meeting, IEDM

Volumn 1991-January, Issue , 1991, Pages 93-96

  Shida, A ^a   Kagamihara, M ^a   Komatsu, M ^a   Kumagai, K ^a   Hirata, M ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CUTOFF FREQUENCY; ELECTRON DEVICES; RECONFIGURABLE HARDWARE; SEMICONDUCTOR DEVICE TESTING;

CMOS STRUCTURES; COLLECTOR RESISTANCE; N-P-N TRANSISTORS; POLYSILICON EMITTER; PROPAGATION DELAY TIME; SIMPLE STRUCTURES; THIN EPITAXIAL LAYER; VLSI TECHNOLOGY;

BINS;

EID: 4243161824     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.1991.235416     Document Type: Conference Paper

References (0)