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Volumn 1, Issue 1, 1996, Pages 102-122

Series-parallel functions and fpga logic module design

Author keywords

Field programmable gate arrays; Series parallel technology mapping; Tree based technology mapping algorithm; Universal logic modules 7

Indexed keywords


EID: 4243111024     PISSN: 10844309     EISSN: None     Source Type: Journal    
DOI: 10.1145/225871.225891     Document Type: Article
Times cited : (3)

References (19)
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    • (1993) Data Book
  • 5
    • 0028259317 scopus 로고
    • An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs
    • CONG J. AND DlNG, Y. 1994. An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs. IEEE Trans. CAD/ICAS 13, 1 (Jan.), 1-12.
    • (1994) IEEE Trans. CAD/ICAS 13, 1 (Jan.) , pp. 1-12
    • Cong, J.1    Dlng, Y.2
  • 8
    • 0026174956 scopus 로고
    • Amap: A technology mapper for selector-based field-programmable gate arrays
    • ACM
    • KARPLUS, K. 1991a. Amap: A technology mapper for selector-based field-programmable gate arrays. In Proceedings ofDAC, ACM, 244-247.
    • (1991) Proceedings OfDAC , pp. 244-247
    • Karplus, K.1
  • 9
    • 0026175483 scopus 로고
    • A technology mapper for table-lookup field-programmable gate arrays
    • ACM
    • KABPLUS, K. 1991b. A technology mapper for table-lookup field-programmable gate arrays. In Proceedings ofDAC, ACM, 240-243.
    • (1991) Proceedings OfDAC , pp. 240-243
    • Kabplus, K.1
  • 12
    • 0026992960 scopus 로고
    • An improved synthesis algorithm for multiplexer-based PGAs
    • ACM
    • MURGAI, R., BRAYTON, R. K, AND SANGIOVANNI-VINCENTELLI, A. L. 1992. An improved synthesis algorithm for multiplexer-based PGAs. In Proceedings ofDAC, ACM, 380-386.
    • (1992) Proceedings OfDAC , pp. 380-386
    • Murgai, R.1    Brayton, R.K.2
  • 14
    • 0015672921 scopus 로고
    • Optimal and near-optimal universal logic modules with interconnected external terminals
    • PATT, Y. N. 1973. Optimal and near-optimal universal logic modules with interconnected external terminals. IEEE Trans. Comput. C-22, 10 (Oct.), 903-907.
    • (1973) IEEE Trans. Comput. C-22, 10 (Oct.) , pp. 903-907
  • 17
    • 0003623384 scopus 로고
    • Logic synthesis for VLSI design. U.C. Berkeley
    • RUDELL, R. L. 1989. Logic synthesis for VLSI design. U.C. Berkeley, Ph.D. thesis, April.
    • (1989) Ph.D. Thesis, April
    • Rudell, R.L.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.