Experimental analysis of above-IC inductor performance with different patterned ground shield configurations and dummy metals

Proceedings of the 36th European Microwave Conference, EuMC 2006

Volumn , Issue , 2006, Pages 40-43

  Sun, X ^a   Carchon, G ^a   Kita, Y ^b   Chiba, K ^b   Tani, T ^b   De Raedt, W ^a  

^a IMEC   (Belgium)

^b OKI ELECTRIC INDUSTRY CO   (Japan)

Author keywords

Above IC inductors; Patterned ground shield; Q factors

Indexed keywords

COMPUTER SIMULATION; ELECTRIC INDUCTORS; NATURAL FREQUENCIES;

CENTER GROUND SHIELD (CGS); PATTERNED GROUND SHIELD; Q-FACTORS;

INTEGRATED CIRCUITS;

EID: 41649113934     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EUMC.2006.281176     Document Type: Conference Paper

References (6)

1. G. Carchon et al., "Wafer Level Packaging Technology for Low-Loss On-chip Transmission Lines and Inductors," PP. 167-168. International Microelectronics and packaging Society 2003 (IMAPS 2003), Boston, MA, November 16-20, 2003.
2. X. Sun et al., "High-Q On-chip Inductors using Thin- Film Wafer Level Packaging Technology Demonstrated on a 90nm RF-CMOS 5GHz VCO", 35th EUMW, OCT. 2005. pp. 77-80.
3. G. Carchon et al., " Thin-Film as Enabling Passive Integration Technology for RF SoC and SiP", 2005 IEEE International Solid-State Circuit Conference (ISSCC), pp.398-399, San Francisco, February 6-10, 2005
4. L. F. Tiemeijer et al., "Record Q symmetrical inductors for 10-GHz LC-VCOs in 0.18-μm gate-length CMOS," IEEE Electron Device Letters, vol. 23, no. 12, pp. 713-715, December 2002.
5. C. P. Yue et al., " On-chip spiral inductors with patterned ground shields for Si-based RFIC's ," IEEE J. Solid-state Circuit, vol.33, pp.743-752, May 1998.
6. C.Detcheverry et al., "The effect of copper design on inductor performance", ESSDERC, Sept. 2003, pp.107-110