An interactive design environment for C-based high-level synthesis of RTL processors

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 16, Issue 4, 2008, Pages 466-475

  Shin, Dongwan ^b   Gerstlauer, Andreas ^a,b   Domer, Rainer ^a,b   Gajski, Daniel D ^a,b  

^a IEEE

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Embedded systems; High level synthesis; Interactive design environment; Register transfer level (RTL) processor; System on chip (SoC)

Indexed keywords

ALGORITHMS; EMBEDDED SYSTEMS; PRODUCT DESIGN; SCHEDULING;

INTERACTIVE DESIGN ENVIRONMENT; REGISTER TRANSFER LEVEL (RTL); SYSTEM ON CHIP (SOC);

PROGRAM PROCESSORS;

EID: 41549166985     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2007.915390     Document Type: Article

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