An UPPAAL model for formal verification of master/slave clock synchronization over the Controller Area Network

IEEE International Workshop on Factory Communication Systems - Proceedings, WFCS

Volumn , Issue , 2006, Pages 3-12

  Rodríguez Navas, Guillermo ^a   Proenza, Julián ^a   Hansson, Hans ^b  

^a UNIVERSITAT DE LES ILLES BALEARS   (Spain)

^b MÄLARDALEN UNIVERSITY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

MATHEMATICAL MODELS; MODEL CHECKING; SYNCHRONIZATION;

CHANNEL FAULTS; CONTROLLER AREA NETWORK; DISTRIBUTED APPLICATIONS; SLAVE CLOCK SYNCHRONIZATION;

ELECTRIC CONTROL EQUIPMENT;

EID: 41549160372     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/wfcs.2006.1704117     Document Type: Conference Paper

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