A single error correction double burst error detection code

Conference Record of the Asilomar Conference on Signals, Systems and Computers

Volumn 1, Issue , 2003, Pages 1118-1121

  Bodnar, Lance ^a   Chapelle, Gregory ^b  

^a VIASAT INC   (United States)

^b NOKIA RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIT ERROR RATE; CODES (SYMBOLS); DATA STORAGE EQUIPMENT; ERROR ANALYSIS; ERROR DETECTION; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; VECTORS;

DATA PROTECTION; ERROR DETECTION CODE; GILBERT-VARSHAMOV BOUND; SINGLE EVENT UPSET (SEU);

ERROR CORRECTION;

EID: 4143121524     PISSN: 10586393     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. Y. Tosaka, S. Satoh, T. Itakura, H. Ehara, T. Ueda, G. Woffinden, S. Wender, "Measurement and Analysis of Neutron-Induced Soft Errors in Sub-Half-Micron CMOS Circuits", IEEE Transactions on Electron Devices, Vol. 45, No. 7, July 1998, pp. 1453-1458.
2. S. Lin and D. Costello, Error Control Coding: Fundamentals and Applications, Prentice-Hall Inc., 1983.
3. US Patent 6519734, "Single bit error correction, double burst error detection technique", February 11, 2003, L. Bodnar and G. Chapelle.
4. US Patent 6536009, "Technique for generating single-bit error-correcting, two-bit burst error detecting codes", March 18, 2003, L. Bodnar.