Build-in reliability analysis for circuit design in the nanometer technology era

2004 International Conference on Integrated Circuit Design and Technology, ICICDT

Volumn , Issue , 2004, Pages 205-210

  Liu, Zhihong ^a   Zhang, Weiquan ^a   Mu, Fuchen ^a  

^a CADENCE DESIGN SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

HOT CARRIER INJECTION (HCI); NANOMETER TECHNOLOGY ERA; NEGATIVE BIAS TEMPERATURE INSTABILITY (NBTI); POTENTIAL CIRCUIT FUNCTION;

COMPUTER AIDED DESIGN; COMPUTER SIMULATION; ELECTRIC POTENTIAL; HOT CARRIERS; MATHEMATICAL MODELS; MOS DEVICES; OPTIMIZATION; PRODUCT DESIGN; RELIABILITY; VLSI CIRCUITS;

ELECTRIC NETWORK ANALYSIS;

EID: 4143069238     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (17)

1. B.E. Deal et al., J. Electrochem. Soc. Vol. 114(3). 266. 1967
2. K. Saminadayer and J C Pfister, Solid State Electronics. Vol 20, 891., 1977
3. Sanjay Rangan et al. IEDM 2003.
4. Anand T Krishnan et al. IEDM 2003
5. M A Alam, IEDM 2003
6. YungHuei Lee et al, IEDM 2003
7. Toyoji Yamamoto, TED Vol46. pp921-926, No.5, May 1999
8. G. La Rosa et al. Proceeding of IEEE 35th International Reliability Physics Symposium, pp.282, 1997
9. Lifeng Wu, ISQED 2003
10. N. Koike and K. Tatsuuma, "A Drain Avanlanche Hot Carrier Lifetime Model for n- and p-Channel MOSFET's," in Proc. IEEE IRPS, p. 86, 2002
11. R. Tu, E. Rosenbaum, W. Chan, C. Li, E. Minami, K. Quader, P. Ko, and C. Hu, "Berkeley Reliability Tools - BERT", IEEE Trans. CAD IC System, Vol.12, No. 10, p. 1524, 1993
12. C. Hu, S. Tam, F. -C. Hsu, P. Ko, T. Chan, and K. Terrill, "Hot-electron induced MOSFET degradation-model, monitor, improvement," IEEE Trans. Electron Devices, vol. ED-32, pp. 375-385, Feb. 1985
13. 2 energy barrier," in IEDM Tech. Dig., 1982
14. T. Horiuchi, H. Mikoshiba, K. Nakamura, and K. Hamano, "A simple method to evaluate device lifetime due to hot-carrier effect under dynamic stress," IEEE Electron Device Letters, vol. EDL-7, p. 337, 1986
15. Yoshiyuki kawakami, DAC 2000, pp289-294
16. Hirokazu Yonezawa, IEDM 1998, pp93-96
17. Giovanni De MIcheli, "Synthesis and Optimization of Digital Circuits", McGraw-Hill, 1994