Fast hardware compilation of behaviors into an FPGA-based dynamic reconfigurable computing system

Proceedings - 12th Symposium on Integrated Circuits and Systems Design, SBCCI 1999

Volumn , Issue , 1999, Pages 150-153

  Cardoso, Joéo M P ^a   Neto, Horácio C ^a  

^a UNIVERSITY OF ALGARVE   (Portugal)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATION THEORY; COMPUTER SOFTWARE; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HIGH LEVEL SYNTHESIS; LOGIC SYNTHESIS; PROGRAM COMPILERS; RECONFIGURABLE HARDWARE; SYSTEMS ANALYSIS;

ARCHITECTURE AND PERFORMANCE; COMPILATION TECHNIQUES; CONTROL UNIT; DYNAMIC RECONFIGURABLE COMPUTING; HARDWARE COMPILATION; RECONFIGURABLE; RECONFIGURABLE DEVICES; RESOURCE SHARING;

RECONFIGURABLE ARCHITECTURES;

EID: 4143066055     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SBCCI.1999.803109     Document Type: Conference Paper

References (18)

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