Trap layer engineered FinFET NAND flash with enhanced memory window

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2006, Pages 88-89

  Ahn, Young Joon ^a   Choe, Jeong Dong ^a   Lee, Jong Jin ^a   Choi, Donguk ^a   Cho, Eun Suk ^a   Choi, Byung Yong ^a   Lee, Se Hoon ^a   Sung, Suk Kang ^a   Lee, Choong Ho ^a   Cheong, Seong Hwee ^a   Lee, Dong Kak ^a   Kim, Seung Beom ^a   Park, Donggun ^a   Ryu, Byung Il ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CHARGE TRAPPING; FLASH MEMORY; GATE DIELECTRICS; NAND CIRCUITS; PERMITTIVITY;

DESIGN PARAMETERS; NANODOT MEMORY DEVICES; TRAP LAYERS;

FIELD EFFECT TRANSISTORS;

EID: 41149173744     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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