Sub-1nm EOT HfSix/HfO2 gate stack using novel Si extrusion process for high performance application

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2006, Pages 166-167

  Ando, T ^a   Hirano, T ^a   Tai, K ^a   Yamaguchi, S ^a   Kato, T ^a   Hagimoto, Y ^a   Watanabe, K ^a   Yamamoto, R ^a   Kanda, S ^a   Nagano, K ^a   Terauchi, S ^a   Tateshita, Y ^a   Tagawa, Y ^a   Saito, M ^a   Iwamoto, H ^a   Yoshida, S ^b   Watanabe, H ^b   Nagashima, N ^a   Kadomura, S ^a  

^a SONY CORPORATION   (Japan)

^b OSAKA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CRYSTALLIZATION; ELECTRON MOBILITY; EXTRUSION; HAFNIUM COMPOUNDS; OPTIMIZATION; SILICON;

GATE STACKS; INTERFACIAL LAYERS; MOBILITY DEGRADATION;

GATES (TRANSISTOR);

EID: 41149155968     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. S. B. Samavedam et al., Tech. Dig. IEDM, p.433, 2002
2. R. Chau, Pro. AVS. 5th. ICMI, p.1, 2004
3. T. Hirano et al., Tech. Dig. IEDM, p.911, 2005
4. K. Goto et al., Tech. Dig. IEDM, p.209, 2004
5. Chun-Yung Sung et al., Tech. Dig. IEDM, p.243, 2005
6. M. Horstmann et al., Tech. Dig. IEDM, p.235, 2005
7. S. Tyagi et al., Tech. Dig. IEDM, p. 1070, 2005