A raised source/drain extension pFET on Si (110) realized by In-situ doped selective epitaxy technology

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2006, Pages 190-191

  Wang, J ^a   Kikuchi, Y ^a   Tateshita, Y ^a   Kato, T ^a   Kataoka, T ^a   Hirano, T ^a   Nagano, K ^a   Ikuta, T ^a   Miyanami, Y ^a   Fujita, S ^a   Hiyama, S ^a   Yamamoto, R ^a   Kanda, S ^a   Yamakawa, S ^a   Kimura, T ^a   Kugimiya, K ^a   Yamagishi, N ^a   Tagawa, Y ^a   Kamide, Y ^a   Iwamoto, H ^a   Ohno, T ^a   Saito, M ^a   Kadomura, S ^a   Nagashima, N ^a   more..

^a SONY CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

HOLE MOBILITY; IONS; REDUCTION; SILICON WAFERS;

DOPED SELECTIVE EPITAXY TECHNOLOGY; DRAIN EXTENSION; PARASITIC RESISTANCE REDUCTION;

FIELD EFFECT TRANSISTORS;

EID: 41149131927     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

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3. Y. Tateshita et al, SSDM, p904 (2005).
4. Y. Kikuchi et al., VLSI-TSA (2006), accepted.
5. H. Wakabayashi et al., IEDM Tech. Dig., p151(2005).
6. H. Nakamura et al, J. J. Appl. Phys. Vol. 43, p1723 (2004).