The European logarithmic microprocessor

IEEE Transactions on Computers

Volumn 57, Issue 4, 2008, Pages 532-546

  Coleman, J Nicholas ^a   Softley, Chris I ^b   Kadlec, Jiri ^c   Matousek, Rudolf ^d   Tichy, Milan ^c   Pohl, Zdenek ^c   Hermanek, Antonin ^c   Benschop, Nico F ^e,f  

^a NEWCASTLE UNIVERSITY   (United Kingdom)

^b Photonfocus AG   (Switzerland)

^c INSTITUTE OF INFORMATION THEORY AND AUTOMATION   (Czech Republic)

^d Spielberg Office Centre   (Czech Republic)

^e PHILIPS RESEARCH LABORATORIES   (Netherlands)

^f NONE   (Netherlands)

Author keywords

Design studies; Emerging technologies; High speed arithmetic; Instruction set design; Logarithmic number system; SIMD processors

Indexed keywords

DIGITAL ARITHMETIC; PIPELINE PROCESSING SYSTEMS; TECHNOLOGY;

HIGH-SPEED ARITHMETIC; INSTRUCTION SET DESIGN; LOGARITHMIC NUMBER SYSTEM;

MICROPROCESSOR CHIPS;

EID: 40949135718     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2007.70791     Document Type: Article

References (13)

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9. J.N. Coleman, C.I. Softley, J. Kadlec, R. Matousek, M. Licko, Z. Pohl, and A. Hermanek, "The European Logarithmic Microprocessor - A QR RLS Application," Proc. 35th IEEE Asilomar Conf. Signals, Systems, and Computers, 2001.
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