FPGA implementation of FastICA based on floating-point arithmetic design for real-time blind source separation

IEEE International Conference on Neural Networks - Conference Proceedings

Volumn , Issue , 2006, Pages 2785-2792

  Shyu, Kuo Kai ^a   Li, Ming Huan ^a  

^a NATIONAL CENTRAL UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

BLIND SOURCE SEPARATION; DIGITAL ARITHMETIC; DIGITAL SIGNAL PROCESSING; INDEPENDENT COMPONENT ANALYSIS;

ARITHMETIC DESIGN; DIGITAL SIGNAL PROCESSING ALGORITHM; KURTOSIS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 40649122044     PISSN: 10987576     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

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4. IEEE Standard for Binary Floating Point Arithmetic, ANSI/IEEE Standard 745-1985, Aug. 1985.
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