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Volumn 18, Issue 3, 2008, Pages 197-199

A 2.4 GHz fully integrated cascode-cascade CMOS doherty power amplifier

Author keywords

CMOS; Efficiency; Fully integrated; Orthogonal frequency division multiplexing (OFDM); Peak to average power ratio (PAPR); Power amplifier (PA); Power back off

Indexed keywords

ELECTRIC LINES; INTEGRATION; MICROPROCESSOR CHIPS; NETWORKS (CIRCUITS); POWER AMPLIFIERS;

EID: 40549121663     PISSN: 15311309     EISSN: None     Source Type: Journal    
DOI: 10.1109/LMWC.2008.916812     Document Type: Article
Times cited : (32)

References (11)
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    • J. Kang, D. Yu, K. Min, and B. Kim, "A ultra-high PAE Doherty amplifier based on 0.13-μm CMOS process," IEEE Microw. Wireless Compon. Lett., vol. 16, no. 9, pp. 505-507, Sep. 2006.
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    • Kang, J.1    Yu, D.2    Min, K.3    Kim, B.4
  • 7
    • 34147094202 scopus 로고    scopus 로고
    • The Doherty power amplifier with on-chip dynamic bias control circuit for handset application
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    • J. Nam and B. Kim, "The Doherty power amplifier with on-chip dynamic bias control circuit for handset application," IEEE Trans. Microw. Theory Tech., vol. 55, no. 4, pp. 633-642, Apr. 2007.
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    • M. Elmala and R. Bishop, "A 90 nm CMOS Doherty power amplifier with integrated hybrid coupler and impedance transformer," in IEEE RFIC Symp. Dig., Jun. 2007, pp. 423-426.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.