An orthogonal simulated annealing algorithm for large floorplanning problems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 12, Issue 8, 2004, Pages 874-876

  Ho, Shinn Ying ^a   Ho, Shinn Jang ^b   Lin, Yi Kuang ^c   Chu, William Cheng Chung ^d  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b NATIONAL FORMOSA UNIVERSITY   (Taiwan)

^c FENG CHIA UNIVERSITY   (Taiwan)

^d TUNGHAI UNIVERSITY   (Taiwan)

Author keywords

Floorplanning; Optimization; Orthogonal experimental design; Simulated annealing; Very large scale integration (VLSI)

Indexed keywords

ALGORITHMS; ANNEALING; BENCHMARKING; OPTIMIZATION; PARAMETER ESTIMATION; PRINTED CIRCUIT BOARDS; PROBLEM SOLVING; WEBSITES;

EFFICIENT GENERATION MECHANISM (EGM); FLOORPLANNING; ORTHOGONAL EXPERIMENTAL DESIGN (OED);

VLSI CIRCUITS;

EID: 4043104116     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2004.831464     Document Type: Article

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