Virtually pipelined network memory

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2006, Pages 197-207

  Agrawal, Banit ^a   Sherwood, Timothy ^a  

^a University of California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

LATENCY MEMORY ACCESSES; MEMORY HIERARCHY DESIGN;

ALGORITHMS; BANDWIDTH; CONFORMAL MAPPING; HIERARCHICAL SYSTEMS; SYSTEMS ANALYSIS;

NETWORK ARCHITECTURE;

EID: 40349116609     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2006.51     Document Type: Conference Paper

References (30)