A 1.41 W H.264/AVC real-time encoder soc for HDTV1080P

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2007, Pages 12-13

  Liu, Zhenyu ^a   Song, Yang ^a   Shao, Ming ^a   Li, Shen ^a   Li, Ngfeng ^a   Ishiwata, Shunichi ^b   Nakagawa, Masaki ^b   Goto, Satoshi ^a   Ikenaga, Takeshi ^a  

^a WASEDA UNIVERSITY   (Japan)

^b TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CMOS INTEGRATED CIRCUITS; DYNAMIC RANDOM ACCESS STORAGE; REAL TIME SYSTEMS; SEMICONDUCTING SILICON;

CMOS TECHNOLOGY; EXTERNAL MEMORY BANDWIDTH; HARDWARE ENGINES; REAL-TIME ENCODERS;

SIGNAL ENCODING;

EID: 39749203476     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2007.4342716     Document Type: Conference Paper

References (4)

1. J. Tanabe, et al., "Visconti: multi-VLIW image recognition processor based on configurable processor", Proc. CICC, pp.185-188, Sept. 2003.
2. Z. Y. Liu, Y. Song, T. Ikenaga, S. Goto,"Low-Pass filter based VLSI oriented variable block size motion estimation algorithm for H.264", Proc. ICASSP, vol.2, pp.253-256, May 2006.
3. K. Kumagai, et al., "System-in-Silicon Architecture and its Application to an H.264/AVC Motion Estimate for 1080HDTV," ISSCC Dig. Tech. Papers, pp. 430-431, Feb., 2006.
4. Y. W. Huang, et al., "A 1.3TOPS H.264/AVC single chip encoder for HDTV applications," ISSCC Dig. Tech. Papers, pp. 128-129, Feb. 2005.