1-cc Computer: Cross-layer integration with 3.4-nW/bps link and 22-cm locationing

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2007, Pages 90-91

  Ono, G ^a,b   Nakagawa, T ^a,b   Fujiwara, R ^a,b   Norimatsu, T ^a,b   Terada, T ^a,b   Miyazaki, M ^a,b   Suzuki, K ^a,b   Yano, K ^a,b   Ogata, Y ^b   Maeki, A ^b   Kobayashi, S ^b,c   Koshizuka, N ^b,c   Sakamura, K ^b,c  

^a HITACHI LTD   (Japan)

^b YRP Ubiquitous Networking Laboratory   (Japan)

^c UNIVERSITY OF TOKYO   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATION THEORY; ELECTRIC CURRENTS; INNOVATION;

COMMUNICATION LOCATION INTEGRATION; CROSS LAYER INTEGRATION; SPIKE CONTROL;

WIRELESS NETWORKS;

EID: 39749197499     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2007.4342778     Document Type: Conference Paper

References (8)

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3. R. Fujiwara, et al., ISCAS. pp. 4497-4500, May. 2005.
4. T. Norimatsu, et al., ESSCIRC, pp. 267-270, Sep. 2005.
5. K. Mizugaki, et al., to be published in RWS. Jan. 2007.
6. Y. H. Chee, et al., VLSI Circutis, pp. 43-44, Jun. 2006.
7. M. Sheets, et al., VLSI Circutis, pp. 212-213, Jun. 2006.
8. T. C. Karalar, et al., SIPS, pp. 89-94, Oct. 2004.