1.047GHz, 1.2V, 90nm CMOS, 2-way VLIW DSP core using saturation anticipator circuit

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2006, Pages 152-153

  Suzuki, H ^a   Takata, H ^a   Shinohara, H ^a   Teraoka, E ^a   Matsuo, M ^a   Yoshida, T ^a   Sato, H ^a   Honda, N ^a   Masui, N ^a   Shimizu, T ^a  

^a RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

LOGIC DEVICES; OPTIMIZATION; VERY LONG INSTRUCTION WORD ARCHITECTURE;

ANTICIPATOR CIRCUITS; CLOCK FREQUENCY; LOGIC STRUCTURE;

CMOS INTEGRATED CIRCUITS;

EID: 39749184810     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. S. Agarwala , et al., "A 600MHz VLIW DSP", Dig. of ISSCC, pp. 56-57, 2002.
2. W. Lee, et al., "A 1-V Programmable DSP for Wireless Communications", IEEE J. of Solid-State Circuit, vol.32, pp. 1766-1776, 1997.
3. H. Sato, "A Dual-Issue RISC Processor for Multimedia Signal Processing", IEICE Trans., E81-C, pp. 1374-1381, 1998.
4. T. Yoshida, et al., "A 2V 250MHz multimedia processor", Dig. of ISSCC, pp.266-267, 1997.
5. H. Suzuki, et al., "Leading-zero anticipatory logic for high-speed floating point addition", IEEE J. of Solid-State Circuit, Vol. 31, pp. 1157 - 1164, 1996.