A low voltage CMOS square law analog multiplier

1999 Southwest Symposium on Mixed-Signal Design, SSMSD 1999

Volumn , Issue , 1999, Pages 5-8

  Tarzm, Tuna B ^a,b,c   Ismai, Mohammed ^d  

^a ISTANBUL TECHNICAL UNIVERSITY   (Turkey)

^b OHIO STATE UNIVERSITY   (United States)

^c TEXAS INSTRUMENTS   (United States)

^d Ohio State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CUTOFF FREQUENCY; ECONOMIC AND SOCIAL EFFECTS; FREQUENCY MULTIPLYING CIRCUITS; LOW POWER ELECTRONICS;

ANALOG MULTIPLIERS; INPUT VOLTAGES; LOW VOLTAGE OPERATION; LOW VOLTAGES; LOW-POWER DISSIPATION; MODEL PARAMETERS; SATURATION REGION; SINUSOIDAL INPUT;

CMOS INTEGRATED CIRCUITS;

EID: 39749179850     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SSMSD.1999.768581     Document Type: Conference Paper

References (5)

1. [l] J. Babanezhad and G.C. Temes, "A 20-V fourquadrant CMOS analog multiplier", IEEE Journal of Solid-state Circuits, pp. 1158-1168, December 1985
2. A. Hyogo, C. Hwang, M. Ismail and K. Sekine, "CMOS analog VLSI composite cell design and its application to high speed multiplier", IEEJ lSt International Analog VLSI Workshop, ECT-97-59, pp. 95-98, The Ohio State University, USA, May 1997
3. S.R. Zarabadi, M. Ismail and C.-C. Hung, "High Performance Analog VLSI Computational Circuits", IEEE Journal of Solid-state Circuits, Vol. 33, No. 4, pp. 644-649, April 1998
4. E. Seevinck and R.F. Wassenaar, "A versatile CMOS linear transconductor/square-law function circuit", IEEE Journal of Solid-state Circuits, VolSC-22, pp. 366-377, June 1987
5. A. Motamed, Low-Voltage Analog VLSI Circuits and Signal Processing, Ph.D. Dissertation, The Ohio State University, Columbus, 1996