Test cost reduction for the AMD™ athlon processor using test partitioning

Proceedings - International Test Conference

Volumn , Issue , 2008, Pages

  Sehgal, Anuja ^a   Fitzgerald, Jeff ^a   Rearick, Jeff ^a  

^a ADVANCED MICRO DEVICES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

OPTIMAL PATTERN SETS; PARTITION BOUNDARIES; WRAPPER CELLS;

COST REDUCTION; DESIGN FOR TESTABILITY; MONOLITHIC INTEGRATED CIRCUITS; PROGRAM DEBUGGING;

MICROPROCESSOR CHIPS;

EID: 39749171263     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TEST.2007.4437562     Document Type: Conference Paper

References (25)