A delay locked loop synchronization scheme for high frequency multiphase hysteretic DC-DC converters

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2007, Pages 26-27

  Li, Pengfei ^a   Bashirullah, Rizwan ^a   Hazucha, Peter ^b   Karnik, Tanay ^b  

^a University of Florida   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

CMOS; DC DC converter; Hysteretic; Multiphase

Indexed keywords

CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; ECHO SUPPRESSION; MAGNETIC HYSTERESIS; PHASE LOCKED LOOPS; SYNCHRONIZATION;

DELAY LOCKED LOOPS; DUTY CYCLE CONTROL LOOPS; HYSTERETIC COMPARATORS; MULTIPHASE HYSTERETIC CONVERTERS;

DC-DC CONVERTERS;

EID: 39749151008     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2007.4342752     Document Type: Conference Paper

References (5)

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