A 6-bit 800-MS/s pipelined A/D converter with open-loop amplifiers

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2006, Pages 134-135

  Shen, Ding Lan ^a   Lee, Tai Cheng ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

Open loop amplifier; Pipelined A D converter

Indexed keywords

AMPLIFIERS (ELECTRONIC); CMOS INTEGRATED CIRCUITS; POWER SUPPLY CIRCUITS;

ACTIVE AREA; OPEN-LOOP AMPLIFIERS; PIPELINED A/D CONVERTER;

VLSI CIRCUITS;

EID: 39749147795     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

1. A. Varzaghani and C.-K. K. Yang, "A 600MS/s, 5-bit pipelined analog-to-digital converter for serial-link applications," in Symposium on VLSI Circuits, Honolulu, June 2004, pp. 276-279.
2. X. Jiang and M.-C. Frank, "A 1-GHz signal bandwidth 6-bit CMOS ADC with power-efficient averaging," IEEE J. SolidState Circuits, vol. 40, pp. 532-535, Feb. 2005.