Simulating L3 caches in real time using hardware accelerated cache simulation (HACS): A case study with SPECint 2000

Proceedings - Symposium on Computer Architecture and High Performance Computing

Volumn 2002-January, Issue , 2002, Pages 108-114

  Watson, M ^a   Flanagan, J K ^a  

^a 3361 TMCB   (United States)

Author keywords

Acceleration; Buffer storage; Computational modeling; Computer aided software engineering; Computer science; Computer simulation; Field programmable gate arrays; Hardware; Laboratories; Probes

Indexed keywords

ACCELERATION; BUFFER STORAGE; COMPUTER AIDED SOFTWARE ENGINEERING; COMPUTER ARCHITECTURE; COMPUTER SCIENCE; COMPUTER SIMULATION; COMPUTER SOFTWARE; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HARDWARE; LABORATORIES; MEMORY ARCHITECTURE; PROBES; SOFTWARE ENGINEERING;

CACHE SIMULATION; CACHE SIMULATORS; COMPUTATIONAL MODEL; HARDWARE-ACCELERATED; MEMORY HIERARCHY; STORAGE REQUIREMENTS; TRACE COLLECTION; TRACE DRIVEN SIMULATION;

COMPUTER HARDWARE;

EID: 39749128857     PISSN: 15506533     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CAHPC.2002.1180766     Document Type: Conference Paper

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