A rapid yield learning flow based on production integrated layout-aware diagnosis

Proceedings - International Test Conference

Volumn , Issue , 2006, Pages

  Keim, Martin ^a   Tamarapalli, Nagesh ^a   Tang, Huaxing ^a   Sharma, Manish ^a   Rajski, Janusz ^a   Schuermyer, Chris ^b   Benware, Brady ^b  

^a MENTOR GRAPHICS CORPORATION   (United States)

^b AGERE SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA REDUCTION; INTEGRATED CIRCUIT LAYOUT; LEARNING SYSTEMS; LOGIC CIRCUITS;

INTEGRATED LAYOUT; LOGIC DIAGNOSIS; PRODUCTION MATERIAL S;

FAILURE ANALYSIS;

EID: 39749125531     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TEST.2006.297715     Document Type: Conference Paper

References (24)