Multiphase-output level shift system used in multiphase PLL for low power application

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2007, Pages 228-229

  Matsumoto, Akinori ^a   Sakiyama, Shiro ^a   Tokunaga, Yusuke ^a   Morie, Takashi ^a   Dosho, Shiro ^a  

^a PANASONIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POWER UTILIZATION; PHASE SHIFT; POWER SUPPLY CIRCUITS; TRANSISTORS;

LEVEL SHIFTER (LS); MULTIPHASE-OUTPUT LEVEL SHIFT SYSTEM (M-LSS); PHASE ACCURACY;

POWER AMPLIFIERS;

EID: 39749083469     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2007.4342729     Document Type: Conference Paper

References (2)

1. Eby G. Friedman and Scott Powell, "Design and Analysis of a Hierarchical Clock Distribution System for Synchronous Standard Cell/Macrocell VLSI," IEEE JSSC, vol. 21, no. 2, pp. 240-246, Apr. 1986.
2. Shiro Dosho, Shiro Sakiyama, Noriaki Takeda, Yusuke Tokunaga and Takashi Morie, "A PLL for a DVD×16 Write System with 63 Output Phases and 32ps Resolution," ISSCC Dig. Tech. Papers, pp. 2422-2423, Feb. 2006.