A PVT-tolerant low-1/f noise dual-loop hybrid PLL in 0.16μm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2006, Pages

  Lee, Hyung Rok ^a   Kim, Ook ^b   Jung, Keewook ^b   Shin, John ^b   Jeong, Deog Kyoon ^a  

^a Seoul National University   (South Korea)

^b Silicon Image Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DUAL-LOOP HYBRID PLL; OFF-CHIP LOOP FILTER COMPONENTS;

BANDWIDTH; DIGITAL FILTERS; PHASE LOCKED LOOPS; VARIABLE FREQUENCY OSCILLATORS;

CMOS INTEGRATED CIRCUITS;

EID: 39549112415     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)