A clock power model to evaluate impact of architectural and technology optimizations - A summary

IEEE Circuits and Systems Magazine

Volumn 3, Issue 3, 2003, Pages 36-39

  Duarte, David E ^a   Vijaykrishnan, N ^b   Irwin, Mary Jane ^b  

^a INTEL CORPORATION   (United States)

^b PENNSYLVANIA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; COMPUTER SIMULATION; DIGITAL CIRCUITS; ENERGY DISSIPATION; LEAKAGE CURRENTS; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; NETWORKS (CIRCUITS); OPTIMIZATION; SYNCHRONOUS MOTORS;

CLOCK POWER MODELS; DISTRIBUTION CIRCUITRY; MEMORY STRUCTURES; PORTABLE DEVICES;

ARCHITECTURAL DESIGN;

EID: 3943093969     PISSN: 1531636X     EISSN: None     Source Type: Journal    
DOI: 10.1109/MCAS.2003.1263398     Document Type: Article

References (0)