Flexible parallel architecture for DVB-S2 LDPC decoders

GLOBECOM - IEEE Global Telecommunications Conference

Volumn , Issue , 2007, Pages 3265-3269

  Gomes, Marco ^a   Falcão, Gabriel ^a   Silva, Vitor ^a   Ferreira, Vitor ^a   Sengo, Alexandre ^a   Falcão, Miguel ^b  

^a UNIVERSITY OF COIMBRA   (Portugal)

^b MIPSABG Chipidea Lda Portugal   (Portugal)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; COMPUTER HARDWARE; CONFORMAL MAPPING; DECODING;

DECODER ARCHITECTURE; DECODER COMPLEXITY;

NETWORK ARCHITECTURE;

EID: 39349100504     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/GLOCOM.2007.619     Document Type: Conference Paper

References (12)

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9. F. Kienle, T. Brack, and N. Wenn, "A Synthesizable IP Core for DVB-S2 LDPC Code Decoding," Design, Automation and Test in Europe (DATE'05), Munich, Germany, 2005.
10. J. Dielissen, A. Hekstra, and V. Berg, "Low cost LDPC decoder for DVB-S2," Design, automation and test in Europe: Designers' forum (DATE'06), Munich, Germany, 2006.
11. M. Gomes, G. Falcão, J. Gonçalves, V. Silva, M. Falcão, and P. Faia, "HDL Library of Processing Units for Generic and DVB-S2 LDPC Decoding," International Conference on Signal Processing and Multimédia Applications (SIGMAP2006), Setúbal, Portugal, 2006.
12. E. Sharon, S. Litsyn, and J. Goldberger, "An efficient message-passing schedule for LDPC decoding," Proceedings of IEEE 23rd Convention of, Electrical and Electronics Engineers in Israel, 2004, pp. 223-226, 2004.