Reconfigurable implementation of wavelet transform on an FPGA-augmented NIOS processor

Canadian Conference on Electrical and Computer Engineering

Volumn , Issue , 2006, Pages 1052-1055

  Hyun, Eugene ^a   Sima, Mihai ^a   Mcguire, Michael ^a  

^a UNIVERSITY OF VICTORIA   (Canada)

Author keywords

Custom instruction; Discrete wavelet transform; FPGA; Lifting scheme; Nios

Indexed keywords

FIELD PROGRAMMABLE GATE ARRAYS (FPGA); IMAGE COMPRESSION; PROGRAM PROCESSORS; SIGNAL ANALYSIS;

CUSTOM INSTRUCTION; LIFTING SCHEME; NIOS;

DISCRETE WAVELET TRANSFORMS;

EID: 39049115673     PISSN: 08407789     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CCECE.2006.277376     Document Type: Conference Paper

References (6)

1. Altera Corporation. "Nios Development Board: Reference Manual, Stratix Professional Edition," Version 1.1, July 2003.
2. M. Vishwanath, R.M. Owens, and M..T. Irwin, "VLSI Architectures for the Discrete Wavelet Transform," IEEE Transaction on Circuits and Systems - II: Analog and Digital Signal Processing, vol. 42, no. 5, pp. 305-316, May, 1995.
3. I. Daubechies, W. Sweldens, "Factoring Wavelet Transforms into Lifting Steps," J. Fourier Anal. Appl., vol. 4, no. 3, pp. 247-269, 1998.
4. A. Jensen, and A.L. Cour-Harbo, RIPPLES IN MATHEMATICS: THE DISCRETE WAVELET TRANSFORM. Berlin: Springer Verlag, 2001.
5. Altera Corporation. "Nios II Custom Instruction User Guide," Version 1.1, December 2004.
6. Altera Corporation. "Profiling Nios II Systems," Version 1.2, February 2006.