A 1.6Gbps digital clock and data recovery circuit

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2006, Pages 603-606

  Hanumolu, Pavan Kumar ^a   Kim, Min Gyu ^a   Wei, Gu Yeon ^b   Moon, Un Ku ^a  

^a Oregon State University   (United States)

^b HARVARD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA RECOVERY CIRCUIT; DIGITAL CLOCK;

DATA REDUCTION; DIGITAL TO ANALOG CONVERSION; ELECTRIC CLOCKS; INTERFACES (COMPUTER); JITTER;

ELECTRIC NETWORK ANALYSIS;

EID: 39049107473     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2006.320829     Document Type: Conference Paper

References (5)

1. J. Cao et al., "OC-192 transmitter and receiver in standard 0.18μm CMOS," IEEE J. Solid-State Circuits, vol. 37, pp. 1768-1780, Dec. 2002.
2. S. Anand, B. Razavi, "A 2.75 Gb/s CMOS clock recovery circuit with broad capture range," ISSCC Dig. Tech. Papers, pp. 214-215, Feb. 2001.
3. R. Walker et al., "A two-chip 1.5-GBd serial link interface," IEEE J. Solid-State Circuits, vol. 27, pp. 1805-1811, Dec. 1992.
4. J. Sonntag, J. Stonick, "A digital clock and data recovery architecture for multi-gigabit/s binary links," Proc. of IEEE CICC, pp. 532-539, Sep. 2005.
5. J. Lee, K. Kundert, B. Razavi, "Analysis and modeling of bang-bang clock and data recovery circuits," IEEE J. Solid-State Circuits, vol. 39, pp. 1571-1580 Sept. 2004.