Behavioral model based simulation methods for charge-pump PLL's

BEC 2006 - 2006 International Baltic Electronics Conference; Proceedings of the 10th Biennial Baltic Electronics Conference

Volumn , Issue , 2006, Pages 111-114

  Rapinoja, Tapio ^a   Stadius, Kari ^a   Halonen, Kari ^a  

^a AALTO UNIVERSITY   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; MAGNETOELECTRIC EFFECTS; MATLAB; METHOD OF MOMENTS; PHASE LOCKED LOOPS; SPICE; SYSTEMS ENGINEERING; TELECOMMUNICATION;

BEHAVIORAL MODELING; BEHAVIOURAL SIMULATIONS; BUILDING BLOCKS; CHARGE PUMP (CP); INTERNATIONAL (CO); LEVEL DESIGN; LONG SIMULATION TIMES; MATLAB ENVIRONMENT; MATLAB SIMULATIONS; PHASE LOCKED LOOPS (PLLS); SHORT TIME; SPICE MACROMODELS; SPICE SIMULATIONS; TIME DOMAIN (OCT); TIME-DOMAIN SIMULATIONS; TRANSISTOR LEVEL DESIGN;

TIME DOMAIN ANALYSIS;

EID: 38949193688     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/BEC.2006.311073     Document Type: Conference Paper

References (8)

1. http://www.mathworks.com/
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4. Dean Banerjee, "PLL Performance, Simulation and Design Handbook 3rd Edition", http://www.national.com/appinfo/wireless/pll_designbook.html
5. Jan Craninckx, "Low-Phase-Noise Fully Integrated CMOS Frequency Synthesizers", Ph.Diss, K.U. Leuven, 1997.
6. Dick Benson, "Analog /Mixed Signal Examples", http://www.mathworks.com/matlabcentral/fileexchan ge/loadFile.do?objectId=1320
7. Tai-Chen Lee and Behzad Razavi, "A Stabilization Technique for Phase-Locked Frequency Synthesizers", IEEE Journal of Solid-State Circuits, vol.38, No.6, pp. 888-894, June 2003.
8. Mark Sitkowski, "The Macro Modeling of Phase Locked Loops for the Spice Simulator", IEEE Circuits and Devices Magazine, pp. 11-15, March 1991.