Aggressive snoop reduction for synchronized producer-consumer communication in energy-efficient embedded multi-processors

CODES+ISSS 2007: International Conference on Hardware/Software Codesign and System Synthesis

Volumn , Issue , 2007, Pages 245-250

  Yu, Chenjie ^a   Peter Petrov, Peter ^a  

^a UNIVERSITY OF MARYLAND   (United States)

Author keywords

Cache coherence; Embedded systems; Low power multiprocessor system

Indexed keywords

CACHE MEMORY; COMPUTER ARCHITECTURE; MULTIPROCESSING SYSTEMS; NETWORK PROTOCOLS; PROBLEM SOLVING;

COHERENCE PROTOCOLS; HARDWARE ARCHITECTURE; LOW-POWER MULTIPROCESSOR SYSTEM;

EMBEDDED SYSTEMS;

EID: 38849204137     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1289816.1289876     Document Type: Conference Paper

References (11)

1. Jim Nilsson, Anders Landin and Per Stenstrom, "The Coherence Predictor Cache: A Resource-Efficient and Accurate Coherence Prediction Infrastructure", in ISPDP, 2003.
2. M. Ekman, F. Dahlgren and P. Stenstrom, "TLB and snoop energy-reduction using virtual caches in low-power chip-microprocessors", in ISLPED, pp. 243-246, August 2002.
3. M. Loghi, M. Letis, L. Benini and M. Poncino, "Exploring the energy efficiency of cache coherence protocols in single-chip multi-processors", in GLSVLSI, pp. 276-281, 2005.
4. A. Moshovos, G. Memik, A. Choudhary and B. Falsafi, "JETTY: Filtering Snoops for Reduced Energy Consumption in SMP Servers", in HPCA, 2001.
5. A. Moshovos, "RegionScout: Exploiting Coarse Grain Sharing in Snoop-Based Coherence", in ISCA, 2005.
6. T. F. Wenisch, S. Somogyi, N. Hardavellas, J. Kim, A. Ailamaki and B. Falsafi, "Temporal Streaming of Shared Memory", in ISCA, 2005.
7. C. Lee, M. Potkonjak and W. H. Mangione-Smith, "Medi-aBench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems", in 30th MICRO, pp. 330-335, December 1997.
8. M.R Guthaus, J. S. Ringenberg, D. Ernst, T.M. Austin, T. Mudge and R.B. Brown, "MiBench: A free, commercially representative embedded benchmark suite", in WWC, pp. 3-14, Dec 2001.
9. N. Binkert, R. Dreslinski, L. Hsu, K. Lim, A. Saidi and S. Reinhardt, "The M5 Simulator: Modeling Networked Systems", IEEE Micro, vol. 26, n. 4, pp. 52-60, 2006.
10. D. Tarjan, S. Thoziyoor and N. Jouppi, "CACTI 4.0: An Integrated Cache Timing, Power and Area Model", Technical report, HP Laboratories Palo Alto, June 2006.
11. R. Bashirullah, W. Liu and R. Cavin, "Low-power design methodology for an on-chip bus with adaptive bandwidth capability", in DAC, pp. 628-633, 2003.