-
2
-
-
15844425093
-
Nonphotolithographic Nanoscale Memory Density Prospects
-
March
-
A. DeHon, S.C. Goldstein, P.J. Kuekes and P. Lincoln, "Nonphotolithographic Nanoscale Memory Density Prospects," IEEE Transactions on Nanotechnology, vol. 4, no. 2, pp. 215-228, March 2005.
-
(2005)
IEEE Transactions on Nanotechnology
, vol.4
, Issue.2
, pp. 215-228
-
-
DeHon, A.1
Goldstein, S.C.2
Kuekes, P.J.3
Lincoln, P.4
-
4
-
-
85165857852
-
-
R. M. P. Rad and M. Tehranipoor, A New Hybrid FPGA With Nanoscale Clusters and CMOS Routing, submitted to Design Automation Conf. (DAC'06), 2006.
-
R. M. P. Rad and M. Tehranipoor, "A New Hybrid FPGA With Nanoscale Clusters and CMOS Routing," submitted to Design Automation Conf. (DAC'06), 2006.
-
-
-
-
5
-
-
85015357431
-
Nanowire-based Programmable Architectures
-
July
-
A. DeHon, "Nanowire-based Programmable Architectures," ACM Journal on Emerging Technologies in Computing Systems, vol. 1, no. 2, pp 109-162, July 2005.
-
(2005)
ACM Journal on Emerging Technologies in Computing Systems
, vol.1
, Issue.2
, pp. 109-162
-
-
DeHon, A.1
-
6
-
-
24344460925
-
NANOLAB-a tool for evaluating reliability of defect-tolerant nano-architectures
-
July
-
D. Bhaduri, S. Shukla, "NANOLAB-a tool for evaluating reliability of defect-tolerant nano-architectures," IEEE Transactions on Nanotechnology, vol. 4, no. 4, pp. 381-394, July 2005.
-
(2005)
IEEE Transactions on Nanotechnology
, vol.4
, Issue.4
, pp. 381-394
-
-
Bhaduri, D.1
Shukla, S.2
-
7
-
-
18744397824
-
Defect-tolerant interconnect to nanoelectronic circuits: Internally redundant demultiplexers based on error-correcting codes
-
P. Kuekes, W. Robinett, G. Seroussi and R. S. Williams, "Defect-tolerant interconnect to nanoelectronic circuits: internally redundant demultiplexers based on error-correcting codes," Inst. of Phys. Nanotechnology, issue 16, pp. 869-882, 2005.
-
(2005)
Inst. of Phys. Nanotechnology
, Issue.16
, pp. 869-882
-
-
Kuekes, P.1
Robinett, W.2
Seroussi, G.3
Williams, R.S.4
-
8
-
-
0031362699
-
-
B. Culbertson, R. Amerson, R. Carter, P. Kuekes and G. Snider, Defect Tolerance on the Teramac Custom Computer, in Proc. IEEE Symp. on FPGA's for Custom Computing Machines (FCCM'97), pp. 116-123, 1997.
-
B. Culbertson, R. Amerson, R. Carter, P. Kuekes and G. Snider, "Defect Tolerance on the Teramac Custom Computer," in Proc. IEEE Symp. on FPGA's for Custom Computing Machines (FCCM'97), pp. 116-123, 1997.
-
-
-
-
9
-
-
24344437274
-
Seven Strategies for Tolerating Highly Defective Fabrication
-
A. DeHon and H. Naeimi, " Seven Strategies for Tolerating Highly Defective Fabrication," IEEE Design & Test of Computers, vol. 22, Issue 4, pp. 306-315, 2005.
-
(2005)
IEEE Design & Test of Computers
, vol.22
, Issue.4
, pp. 306-315
-
-
DeHon, A.1
Naeimi, H.2
-
11
-
-
18144425202
-
-
J. G. Brown and R. D. S. Blanton, CAEN-BIST: Testing the Nanofabrics, in Proc. Int. Test Conf. (ITC'04), pp. 462-471, 2004.
-
J. G. Brown and R. D. S. Blanton, "CAEN-BIST: Testing the Nanofabrics," in Proc. Int. Test Conf. (ITC'04), pp. 462-471, 2004.
-
-
-
-
12
-
-
0142184735
-
-
M. Mishra and S. C. Goldstein, Defect Tolerance at the End of the Roadmap, in Proc. Int. Test Conf. (ITC'03), pp. 1201-1210, 2003.
-
M. Mishra and S. C. Goldstein, "Defect Tolerance at the End of the Roadmap," in Proc. Int. Test Conf. (ITC'03), pp. 1201-1210, 2003.
-
-
-
-
14
-
-
33847124358
-
Using Built-In Self-Test and Adaptive Recovery for Defect Tolerance in Molecular Electronics-Based Nanofabrics
-
to appear in
-
Z. Wang and K. Chakrabarty, "Using Built-In Self-Test and Adaptive Recovery for Defect Tolerance in Molecular Electronics-Based Nanofabrics," to appear in Int. Test Conf. (ITC'05), 2005.
-
(2005)
Int. Test Conf. (ITC'05)
-
-
Wang, Z.1
Chakrabarty, K.2
-
15
-
-
28444440223
-
-
M. B. Tahoori, Defects, Yield, and Design in Sublithographic Nano-electronics, in proc. Defect and Fault Tolerance in VLSI Systems (DFT'05), pp. 3-11, 2005.
-
M. B. Tahoori, "Defects, Yield, and Design in Sublithographic Nano-electronics," in proc. Defect and Fault Tolerance in VLSI Systems (DFT'05), pp. 3-11, 2005.
-
-
-
-
16
-
-
33751109027
-
SCT: An Approach For Testing and Configuring Nanoscale Devices
-
to appear in
-
R. M. P. Rad and M. Tehranipoor, "SCT: An Approach For Testing and Configuring Nanoscale Devices," to appear in VLSI test Symp., VTS'06, 2006.
-
(2006)
VLSI test Symp., VTS'06
-
-
Rad, R.M.P.1
Tehranipoor, M.2
-
17
-
-
84870027052
-
-
J. L. Kouloheris and A. E. Gamal, PLA-based FPGA Area versus Cell Granularity, in proc. IEEE Custom Integrated Circuits Conferenc, pp. 4.3.1-4.3.4, 1992.
-
J. L. Kouloheris and A. E. Gamal, "PLA-based FPGA Area versus Cell Granularity," in proc. IEEE Custom Integrated Circuits Conferenc, pp. 4.3.1-4.3.4, 1992.
-
-
-
-
18
-
-
0038161696
-
High performance silicon nanowire field effect transistors
-
Y. Cui, Z. Zhong, D. Wang, W U. Wang, and C. M. Lieber, "High performance silicon nanowire field effect transistors," Nanoletters, vol. 3, no. 2, pp. 149-152, 2003.
-
(2003)
Nanoletters
, vol.3
, Issue.2
, pp. 149-152
-
-
Cui, Y.1
Zhong, Z.2
Wang, D.3
Wang, W.U.4
Lieber, C.M.5
-
19
-
-
2142660781
-
The Effect of LUT and Cluster Size on Deep-Submicron FPGA Performance and Density
-
March
-
E. Ahmed and J. Rose, "The Effect of LUT and Cluster Size on Deep-Submicron FPGA Performance and Density," IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 3, pp. 288-298, March 2004.
-
(2004)
IEEE Trans. on Very Large Scale Integration (VLSI) Systems
, vol.12
, Issue.3
, pp. 288-298
-
-
Ahmed, E.1
Rose, J.2
-
20
-
-
0003934798
-
Sis: A system for sequential circuit synthesis
-
Berkeley, CA
-
E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. R. Stephan,R. K. Brayton and A. Sangiovanni-Vincentelli, "Sis: A system for sequential circuit synthesis," UCB/ERL M92/41 (May) University of California, Berkeley, CA, 1992.
-
(1992)
UCB/ERL M92/41 (May) University of California
-
-
Sentovich, E.M.1
Singh, K.J.2
Lavagno, L.3
Moon, C.4
Murgai, R.5
Saldanha, A.6
Savoj, H.7
Stephan, P.R.8
Brayton, R.K.9
Sangiovanni-Vincentelli, A.10
-
21
-
-
0003647211
-
Logic Synthesis and Optimization Benchmarks, Microelectronics Centre of North Carolina
-
Tech. Report
-
S. Yang, " Logic Synthesis and Optimization Benchmarks, Microelectronics Centre of North Carolina," Tech. Report, 1991.
-
(1991)
-
-
Yang, S.1
|