Combined software and hardware techniques for the design of reliable IP processors

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 2006, Pages 265-273

  Rebaudengo, M ^a   Sterpone, L ^a   Violante, M ^a   Bolchini, C ^b   Miele, A ^b   Sciuto, D ^b  

^a POLITECNICO DI TORINO   (Italy)

^b POLITECNICO DI MILANO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

FAULT COVERAGE; FAULT INJECTION ANALYSIS; IP PROCESSORS; PROCESSOR ARCHITECTURE;

FAULT DETECTION; HARDWARE; PROGRAM PROCESSORS; REDUNDANCY;

INTERNET PROTOCOLS;

EID: 38749131599     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DFT.2006.18     Document Type: Conference Paper

References (10)

1. Z. Alkhalifa, V. S. S. Nair, N. Krishnamurthy, and J. A. Abraham. Design and evaluation of system-level checks for on-line control flow error detection. IEEE Trans. Parallel Distrib. Syst., 10(6):627-641, 1999.
2. P. Bernardi, L. Bolzani, M. Rebaudengo, M. Sonza Reorda, and M. Violante. An integrated approach for increasing the soft-error detection capabilities in SoCs processors. In Proc. 20th IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems, pages 445-453, 2005.
3. C. Bolchini, A. Miele, L. Pomante, F. Salice, and D. Sciuto. Reliable system co-design: The FIR case study. In Proc. 19th IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems, pages 433-441, Cannes, France, 2004.
4. C. Bolchini, A. Miele, F. Salice, and D. Sciuto. A model of soft error effects in generic ip processors. In Proc. 20th IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems, pages 334-342, 2005.
5. C. Bolchini, L. Pomante, F. Salice, and D. Sciuto. Reliable system specification for self-checking datapaths. In Proc. of the Conf. on Design, Automation and Test in Europe, pages 1278-1283, Washington, DC, USA, 2005. IEEE Computer Society.
6. P. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, and M. Violante. An FPGA-Based approach for speeding-up fault injection campaigns on safety-critical circuits. Journal of Electronic Testing: Theory and Applications, 18(3):261-271, June 2002.
7. F. Ziegler et al. Terrestrial cosmic rays and soft errors. IBM Journal of Research and Development, 40(1), 1996.
8. O. Goloubeva, M. Rebaudengo, M.S. Reorda, and M. Violante. Improved software-based processor control-flow errors detection technique. In Reliability and Maintainability Symposium, 2005. Proceedings. Annual, pages 583-589, 2005.
9. J. Gaisler. The LEON2 IEEE-1754 (SPARC V8) Processor, 2003. http://www.gaisler.com.
10. M. Rebaudengo, M. Sonza Reorda, M. Torchiano, and M. Violante. Soft-error detection through software fault-tolerance techniques. In Proc. IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems, pages 210-218, 1999.